Synthesizable Vhdl Code Generation from Data Flow Graph

This paper discusses how we generate a VHDL code for a DSP application described in a data ow graph(DFG). Because the generated VHDL code contains only synthesizable constructs and implements details of control logics we can easily transform it into a running hardware module using logic synthesis tools. This facility is very useful for DFG based high level system design tools including our codesign framework PeaCE (Ptolemy extension as Codesign Environment). 1 Introduction In this several years HDLs have gained considerable popularity because they provide hardware designers with software-like development process and help them to complete complex chip design projects successfully. While HDL still plays very important role in system design, there is also increasing need for easier and more intuitive method for system description. Moreover, emerging approaches for high level system design are requiring speciication method of higher level of abstraction than HDL which are biased to hardware model. Among many candidates of higher level speciication methods , data ow graph(DFG) has some attractive merits such as intuitiveness and readability. Many high level system design approaches adopt DFG as system speciication method instead of HDL 1] 2] 3]. Our codesign environment PeaCE (Ptolemy extension as Codesign Environment) which is being developed in Seoul National University also uses a DFG along with VHDL 3]. While we design a digital system based on a DFG representation , we need to generate HDL codes for simulation or synthesis. During simulation stage, because designers are concerned with operation in higher abstraction level, HDL codes can be free from many details of a real system. But the situation is quite diierent in stage of synthesis. Such as register initialization and appropriate clocking should be im